The present invention relates to a dynamic memory and a semiconductor device which uses it, particularly to a dynamic memory suitable for high speed applications with low power consumption and a semiconductor device which uses it.
The operating waveforms of a conventional dynamic memory (hereinafter called DRAM) which stores data in its memory cells each consisting of one n-MOS transistor and one capacitor are as shown in FIGS. 2A and 2B, for example, according to the book about xe2x80x9cVLSI memoriesxe2x80x9d authored by Kiyoo Itoh (published by Baifukan 1994, p. 86). Here, in reading, after word line WL is asserted to read the signal from a memory cell to the bit line BL, /BL, the sense amplifier is activated at a prescribed timing "PHgr"A to amplify the signal on the bit line. As a result, when a row address access time (tRAC) has elapsed after the start of the access, final output of data occurs. A time for rewriting into the memory cell, tRAS, is required before a precharge time (tRP) is needed to precharge the bit line and the like.
The writing sequence is basically similar to the reading sequence; after the sense amplifier is activated, the bit line is activated according to write data to write in a selected memory cell.
This type of dynamic memory needs refresh operation to retain the data in memory cells.
Conventional dynamic memories as mentioned above have the following four problems:
Firstly, for reading, the amplitude of the bit line must be large for rewriting into the memory cell. This means that the cycle time (tRC) as expressed by tRAS+tRP must be long.
Secondly, for writing, non-selected memory cells should operate in the same way as for reading, which also leads to a longer cycle time tRC as in the case of reading operation.
Thirdly, for the above two reasons, if the dynamic memory is fully pipelined, the pipeline pitch must be long.
Fourthly, due to the necessity for refreshing operation, access to the dynamic memory (external access) for purposes other than refreshing and access to it for refreshing compete with each other, resulting in a performance deterioration.
To solve the above-mentioned problems, the present invention provides a semiconductor device which has: a memory circuit which includes plural memory cells provided at intersections of plural bit lines and plural word lines; and an access control circuit which receives an external command and an external address to read data from or write data to the memory circuit at the transition point of a first clock, and supplies them to the memory circuit as an internal command and an internal address to read data from or write data to the memory circuit, at the transition point of a second clock whose frequency is higher than that of the first clock. The access control circuit further has a refresh control circuit which refreshes the plural memory cells at the transition point of the second clock, a timing which does not allow the external command and the external address to be supplied.
Thanks to this configuration, in the memory circuit, even when memory cells require refreshing, the refreshing operation can be isolated from external control as an internal operation so that it can be concealed from outside.